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NB7L585R 2.5V/3.3V, 7GHz/10Gbps Differential 2:1 Mux Input to 1:6 RSECL Clock/Data Fanout Buffer / Translator
Multi-Level Inputs w/ Internal Termination
Description
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The NB7L585R is a differential 1:6 RSECL Clock/Data distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INx inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML, or LVDS logic levels. The NB7L585R produces six identical output copies of Clock or Data operating up to 7 GHz or 10 Gb/s, respectively. As such, NB7L585R is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The NB7L585R is powered with either 2.5 V or 3.3 V supply and is offered in a low profile 5mm x 5mm 32-pin QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB7L585R is a member of the GigaCommTM family of high performance clock products.
Features
1
32
QFN32 MN SUFFIX CASE 488AM
NB7L 585R AWLYYWWG G
A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
+
SEL Q0 VREFAC0 IN0 VT0 IN0 50 W 50 W
* * * * * * * * * * * * * * *
Maximum Input Data Rate > 10 Gb/s Typical Data Dependent Jitter < 10 ps Maximum Input Clock Frequency > 7 GHz Typical Random Clock Jitter < 0.8 ps RMS Low Skew 1:6 RSECL Outputs, 20 ps max 2:1 Multi-Level Mux Inputs 160 ps Typical Propagation Delay 40 ps Typical Rise and Fall Times Differential RSECL Outputs, 400 mV peak-to-peak, typical Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V Internal 50 W Input Termination Resistors VREFAC Reference Output QFN-32 Package, 5mm x 5mm -40C to +85C Ambient Operating Temperature These Devices are Pb-Free and are RoHS Compliant
Q0 Q1 0 Q1 Q2
IN1 VT1 IN1
Q2 Q3 50 W 50 W 1 Q3 Q4
VREFAC1 VCC GND Q4 Q5
Q5
Figure 1. Simplified Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
1
October, 2009 - Rev. 0
Publication Order Number: NB7L585R/D
NB7L585R
GND VCC VCC SEL Q0 Q0 Q1 Q1 Exposed Pad (EP)
Table 1. INPUT SELECT FUNCTION TABLE
SEL* 0 CLK Input Selected IN0 IN1
32 IN0 VT0 VREFAC0 IN0 IN1 VT1 VREFAC1 IN1 1 2 3 4 5 6 7 8 9 GND
31
30
29
28
27
26
25 24 23 22 21 20 19 18 17 GND VCC Q2 Q2 Q3 Q3 VCC GND
1 *Defaults HIGH when left open.
NB7L585R
10 NC
11 VCC
12 Q5
13 Q5
14 Q4
15 Q4
16 VCC
Figure 2. Pinout: QFN-32 (Top View) Table 2. PIN DESCRIPTION
Pin Number 1,4 5,8 2,6 31 10 11, 16, 18 23, 25, 30 29, 28 27, 26 22, 21 20, 19 15, 14 13, 12 9, 17, 24, 32 3 7 - Pin Name IN0, IN0 IN1, IN1 VT0, VT1 SEL NC VCC Q0, Q0 Q1, Q1 Q2,Q2 Q3, Q3 Q4, Q4 Q5, Q5 GND VREFAC0 VREFAC1 EP - - LVTTL/LVCMOS Input - - RSECL Output I/O LVPECL, CML, LVDS Input Pin Description Non-inverted, Inverted, Differential Data Inputs internally biased to VCC/2 Internal 100 W Center-tapped Termination Pin for IN0 / IN0 and IN1 / IN1 Input Select pin; LOW for IN0 Inputs, HIGH for IN1 Inputs; defaults HIGH when left open No Connect Positive Supply Voltage. All VCC pins must be connected to the positive power supply for correct DC and AC operation. Non-inverted, Inverted Differential Outputs Note 1.
Negative Supply Voltage, connected to Ground Output Voltage Reference for Capacitor-Coupled Inputs The Exposed Pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INn/INn input, then the device will be susceptible to self-oscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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NB7L585R
Table 3. ATTRIBUTES
Characteristics ESD Protection RPU - SEL Input Pullup Resistor Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. QFN-32 Oxygen Index: 28 to 34 Human Body Model Machine Model Value > 2 kV > 200 V 37.5 kW Level 1 UL 94 V-0 @ 0.125 in 303
Table 4. MAXIMUM RATINGS
Symbol VCC VIO VINPP IIN Iout IVREFAC TA Tstg qJA qJC Tsol Positive Power Supply Input/Output Voltage Differential Input Voltage |IN - IN| Input Current Through RT (50 W Resistor) Output Current VREFAC Sink or Source Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 4) Thermal Resistance (Junction-to-Case) (Note 4) Wave Solder 0 lfpm 500 lfpm QFN32 QFN32 QFN32 Continuous Surge Parameter Condition 1 GND = 0 V GND = 0 V Condition 2 Rating +4.0 -0.5 to VCC +0.5 1.89 $40 50 100 $1.5 -40 to +85 -65 to +150 31 27 12 265 Unit V V V mA mA mA C C C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7L585R
Table 5. DC CHARACTERISTICS POSITIVE RSECL OUTPUT VCC = 2.375 V to 3.6 V; GND = 0 V; TA = -40C to 85C (Note 5)
Symbol POWER SUPPLY VCC ICC VOH Power Supply Voltage Power Supply Current (Inputs and Outputs Open) VCC = 3.3V VCC = 2.5V 3.0 2.375 3.3 2.5 185 3.6 2.625 225 V mA Characteristic Min Typ Max Unit
RSECL Outputs Output HIGH Voltage (Note 6) VCC = 3.3 V VCC = 2.5 V VCC = 3.3 V VCC = 2.5 V VCC - 1300 2000 1200 VCC - 1800 1500 700 VCC - 1125 2175 1375 VCC - 1525 1775 975 VCC - 1000 2300 1500 VCC - 1350 1950 1150 mV
VOL
Output LOW Voltage (Note 6)
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Note 7) (Figures 5 & 6) VIH VIL Vth VISE VREFAC Single-ended Input HIGH Voltage Single-ended Input LOW Voltage Input Threshold Reference Voltage Range (Note 8) Single-ended Input Voltage (VIH - VIL) Output Reference Voltage @100 mA for Capacitor- Coupled Inputs, Only Vth + 100 GND 1100 200 VCC Vth - 100 VCC -100 VCC - GND VCC - 1150 VCC - 1000 mV mV mV mV
VREFACx (for Capacitor- Coupled Inputs, Only) VCC - 1350 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7 & 8) (Note 9) VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN Differential Input HIGH Voltage (IN, IN) Differential Input LOW Voltage (IN , IN) Differential Input Voltage (IN , IN) (VIHD - VILD) Input Common Mode Range (Differential Configuration, Note 10) (Figure 9) Input HIGH Current IN/IN (VTIN/VTIN Open) Input LOW Current IN/IN (VTIN/VTIN Open) 1200 GND 100 1050 -150 -150 VCC VIHD - 100 1200 VCC - 50 150 150 mV mV mV mV mA mA
CONTROL INPUT (SEL Pin) Input HIGH Voltage for Control Pin Input LOW Voltage for Control Pin Input HIGH Current Input LOW Current 2.0 GND -150 -150 VCC 0.8 150 150 mV mV mA mA
TERMINATION RESISTORS Internal Input Termination Resistor (Measured from INx to VTx) 45 50 55 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. RSECL outputs (Qn/Qn) loaded with 50 W to VCC - 2 V for proper operation. 7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single-ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal.
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NB7L585R
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0 V; TA = -40C to 85C (Note 11)
Symbol fMAX fDATAMAX fSEL VOUTpp tPLH, tPHL tPLH TC tskew tDC FN Characteristic Maximum Input Clock Frequency; VOUTpp w 200 mV Maximum Operating Data Rate (PRBS23) Maximum Toggle Frequency, SEL Output Voltage Amplitude (@ VINPPmin) (Note 12) (Figures 8 and 10) Propagation Delay to Differential Outputs, @ 1 GHz, measured at differential crosspoint Propagation Delay Temperature Coefficient Output - Output skew (within device) (Note 13) Device - Device skew (tpd max - tpdmin) Output Clock Duty Cycle (Reference Duty Cycle = 50%) Phase Noise, fc = 1 GHz fin v 6.0 GHz 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 40 MHz 45 50 -134 -136 -149 -150 -150 -151 36 0.2 2.0 0.8 10 0.7 100 15 40 1200 70 fin 6.0 GHz IN/IN to Q/Q SEL to Q Min 6 8 1.0 200 100 Typ 7 10 1.5 400 160 200 50 20 100 55 225 300 Max Unit GHz Gbps GHz mV ps Dfs/C ps % dBc
t FN tJITTER
Integrated Phase Jitter (Figure x) fc = 1 GHz, 12 kHz * 20 MHz Offset (RMS) RJ - Output Random Jitter (Note 14) DJ - Residual Output Deterministic Jitter (Note 15) Crosstalk Induced Jitter (Adjacent Channel) (Note 17) fin 5.0 GHz 8 Gbps
fs ps RMS ps pk-pk ps RMS mV ps
VINPP tr,, tf
Input Voltage Swing (Differential Configuration) (Note 16) Output Rise/Fall Times @ 1 GHz (20% - 80%), Q, Q
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 400 mV pk-pk source, 50% duty cycle clock source. All output loading with external 50 W to VCC - 2 V. Input edge rates 40 ps (20% - 80%). 12. Output voltage swing is a single-ended measurement operating in differential mode. 13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from cross-point of the inputs to the crosspoint of the outputs. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Additive Peak-to-Peak data dependent jitter with input NRZ data at PRBS23. 16. Input voltage swing is a single-ended measurement operating in differential mode. 17. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs. 500 OUTPUT VOLTAGE AMPLITUDE (mV) Q AMP (mV) 400 300 200 100 0
0
1
2
3
4
5
6
7
8
Figure 3. Clock Output Voltage Amplitude (VOUTpp) vs. Input Frequency (fin) at Ambient Temperature (Typical)
fin, CLOCK INPUT FREQUENCY (GHz)
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NB7L585R
VIH INx 50 W VTx 50 W INx Vth Vth VIL
IN
IN
Figure 4. Input Structure
Figure 5. Differential Input Driven Single-Ended
VCC Vthmax
VIHmax VILmax IN VIH Vth VIL VIHmin VILmin IN
Vth Vthmin VEE
IN
Figure 6. Vth Diagram
Figure 7. Differential Inputs Driven Differentially
VCC VCMRmax VID = |VIHD(IN) - VILD(IN)| VIHD VILD VCMRmin IN VCMR IN
VIHDmax VILDmax VIHDtyp VILDtyp VIHDmin VILDmin
VID = VIHD - VILD
IN IN
VEE
Figure 8. Differential Inputs Driven Differentially
Figure 9. VCMR Diagram
IN VINPP = VIH(IN) - VIL(IN) IN Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH Qx Qx SEL
VCC / 2
VCC / 2
tpd
tpd
Figure 10. AC Reference Measurement
Figure 11. SEL to Qx Timing Diagram
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NB7L585R
VCC VCC VCC VCC
Zo = 50 W LVPECL Driver VT = VCC - 2.0 V
NB7L585R IN 50 W 50 W LVDS Driver
Zo = 50 W VT = OPEN
NB7L585R IN 50 W 50 W
Zo = 50 W CLKx GND
IN
Zo = 50 W CLKx GND GND
IN
GND
Figure 12. LVPECL Interface
Figure 13. LVDS Interface
VCC
VCC
VCC
VCC
Zo = 50 W CML Driver VT = VCC
NB7L585R IN 50 W 50 W Differential Driver
Zo = 50 W VT = VREFAC*
NB7L585R IN 50 W 50 W
Zo = 50 W
IN
Zo = 50 W
IN
GND
GND
GND
GND
Figure 14. Standard 50 W Load CML Interface
Figure 15. Capacitor-Coupled Differential Interface (VT Connected to VREFAC)
*VREFAC bypassed to ground with a 0.01 mF capacitor.
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 16. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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NB7L585R
DEVICE ORDERING INFORMATION
Device NB7L585RMNG NB7L585RMNR4G Package QFN-32 (Pb-Free) QFN-32 (Pb-Free) Shipping 74 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB7L585R
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 488AM-01 ISSUE O
D
A B
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X 9 8
32 X b 0.10 C A B
0.05 C BOTTOM VIEW 0.28
32 X 28 X
GigaComm is a trademark of Semiconductor Component Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE EE
TOP VIEW SIDE VIEW D2
16 17 1 32 25
PIN ONE LOCATION
E
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
(A3) A A1 C
EXPOSED PAD SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
SOLDERING FOOTPRINT*
5.30 3.20
K
32 X
E2
24
0.63
32 X
e
3.20
5.30
0.50 PITCH
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NB7L585R/D

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